New Electronics

Faster FPGA verification

Launched in 2015, and used by about 20% of all VHDL FPGA designers, UVVM is one of the fastest growing verification methodologies in the EDA industry. Today, design verification accounts for more than ...
Semiconductor Engineering

FPGA VHDL Verification

This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented ...
EDN

VHDL 101 – Hierarchy in VHDL Code

All designs need structure to make them easy to develop and maintain. We all use abstraction in our designs regardless of if it being electronics, software, or mechanical. In this article we will look ...
Hackaday

Slice Your Next FPGA Design

A recent trend has been to convert high-level constructs into FPGA code like Verilog or VHDL. Silice goes the other way: it converts very hardware-specific concepts to Verilog and aims to be a more ...
EDN

VHDL 101 – IF, CASE, and WHEN in a Process

Last time, in the third installment of VHDL we discussed logic gates and Adders. Let’s move on to some basic VHDL structure. All HDL languages bridge what for many feels like a strange brew of ...
Hackaday

FPGA Snake Game Uses No VHDL At All

We’re really not supposed to start a feature like this; but this hack is awesome. It’s a game of Snake implemented by an FPGA dev board. It uses a 16×16 LED matrix as the display and an SNES ...
Electronic Design

FPGA Design Flow Takes Simulink Code Into Synthesis

Thanks to collaboration between The MathWorks and Mentor Graphics, MathWorks’ Simulink HDL Coder users gain a smooth path into synthesis. Mentor’s Precision Synthesis tool now supports HDL generated ...