NanoIC pilot line announces the release of the N2 P-PDK v1.0, an important update of its N2 Pathfinding Process Design Kit (P ...

“AI chips commonly employ SRAM memory as buffers for their reliability and speed, which contribute to high performance. However, SRAM is expensive and demands significant area and energy consumption.

NanoIC’s updated P-PDK aims to address this challenge by offering instant access to realistic design features. The inclusion of SRAM macros allows users to move beyond simple logic design and ...

Experts at the Table — Part 2: Semiconductor Engineering sat down to talk about AI and the latest issues in SRAM with Tony Chan Carusone, chief technology officer at Alphawave Semi; Steve Roddy, chief ...

In this post, we are going to explain the differences between SRAM and DRAM. These are types of RAM (Random Access Memory) which is an internal memory of a computer. Now, if you are curious about ...

Anita Farokhnejad, DTCO Program Manager and Julien Ryckaert, VP R&D, both at imec, discuss the recent NanoIC pilot line announcement - the release of the N2 P-PDK v1.

Startup launches “Corsair” AI platform with Digital In-Memory Computing, using on-chip SRAM memory that can produce 30,000 tokens/second at 2 ms/token latency for Llama3 70B in a single rack. Using ...