Semiconductor Engineering

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
Semiconductor Engineering

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips

A new technical paper titled “HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips” was published by researchers at ETH Zürich, TOBB University of Economics and ...
TweakTown

China's Innosilicon LPDDR6/5X memory controller IP delivered to first customers, up to 14.4Gbps

Chinese chip maker Innosilicon has announced its new LPDDR6/5X memory controller IP provided to its first customers in China, ...
EDN

Motorola may integrate DRAM controller into PowerPC

SAN MATEO, Calif. — To maximize data bandwidth and reduce memory latency, Motorola Inc. said it will likely integrate a DRAM controller directly onto a future high-end PowerPC processor — a trend that ...
EDN

DRAM controller throughput may be the next key to SoC performance

As SoC architects make the transition from CPU-centric designs with a single major processor to multiprocessing designs in which many processing peers carry on in parallel, efficient use of external ...
Forbes

Spin Memory Selector Improves DRAM, ReRAM And MRAM Density, New Microchip SSD Controller

Spin Memory, a magnetic random-access memory (MRAM) startup announced a new semiconductor technology that could allow a dramatic improvement in DRAM as well as emerging memory technologies, such as ...