Design-Reuse

Handling Asynchronous Clock Groups in SDC

Most SoC designs in today's world employ multiple clocks and commonly have many clock domains. As data crosses from one clock domain to another within the design, the potential for metastability ...
Design-Reuse

Asynchronous Logic: large CMOS devices without a clock tree

CMOS is, and will continue to be, the work-horse process technology of the semi-conductor industry. But designers of large devices, of complex SoCs and of devices using multiple IP elements are ...
EDN

Make an asynchronous clock for VPX-based PCIe systems

The VITA46 VPX standarddefines a chassis that can accommodateall manner of cards with a commonform factor (Reference 1). Thecards plug into a common backplane.This design employs the VITA46.4standard ...
Embedded

FPGA Clock Schemes

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.