Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

Editor's Note: In Part 3 of this series, consultant and ASIC designer Tom Moxon covered several RTL and logic synthesis design flows. In this installment of the series, he'll describe new physical ...

D.E. Shaw Research is seeking a Physical Design Engineer in our Job of the Week. Unusually intelligent and accomplished ASIC physical design engineers are sought to join a New York-based ...